Method and system of decoding an encoded data block

ABSTRACT

A method and system of decoding data including a padding unit, interleaver unit and decoder. A block of data symbols where each data symbol represents an encoded data bit, is received by the padding unit. The padding unit determines if the block data symbols has a number of data symbols equal to a threshold value M. If the number of data symbols is less than M, the padding unit pads the block of data symbols with at least one padding symbol. The decoder decodes the padded block of data symbols.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a method and system of decoding datablocks of transmitted signals and in particular, turbo decoding.

[0003] 2. Description of the Prior Art

[0004] Decoders and their related encoders are typically used in signalprocessing. There are various forms of encoders and decoders. Oneexample of an encoder is a convolution encoder. Examples of decodersinclude Viterbi and turbo decoders. However, other encoders and decodersare well known in the art. The decision to use a particular decoder isgenerally based on the performance and complexity constraints imposed bya system.

[0005] In some decoding situations, regardless of the type of decoderthat is selected, the minimum number of data bits in a data blockrequired for the selected decoder to function properly may varydepending upon the hardware which embodies the decoder. For example, adecoder may have a minimum bit recognition requirement of a certainnumber of bits and fail to recognize a data block of less than thecertain number of bits.

SUMMARY

[0006] In a method and system for decoding an encoded data block havinga number of data symbols N less than the minimum number of data symbolsM required for proper operation of the decoder, a padding unit countsthe number of data symbols N in an encoded data block and determines ifthe number of data symbols is less than M. If the number of data symbolsN is not less than M, the padding unit allows the encoded data block topass through the padding unit unchanged and the decoder functions as iswell known in the art.

[0007] If the number of data symbols N in an encoded data block is lessthan M then the padding unit pads the encoded data block by adding anumber of padding symbols X to the data symbols so that N+X=M. Thepadding symbols may be placed into the buffer in various positionsincluding front padding, back padding, middle padding or any othermethod known in the art. Additionally, the padding unit notifies aninterleaving processor that padding is occurring and the number of datasymbols N and position of padding symbols.

[0008] The interleaver processor stores a padded interleaving tablecorresponding to each possible arrangement of data symbols and paddingsymbols and outputs a padded interleaver table to the padding unitcorresponding to the padded encoded data block.

[0009] The padding unit transfers the padded interleaver table andassociated padded encoded data block to the decoder. The decoder whichmay be a turbo decoder or other decoder well known in the art, functionsas is well known in the art and the use of the padding symbols simplytricks the decoder into decoding a number of data symbols less than M.

[0010] Thus, by using the padding symbols, the decoder properly decodesdata blocks containing less than M data symbols.

BRIEF DESCRIPTION OF THE FIGURES

[0011] The present invention will become more fully understood from thedetailed description given herein below and the accompanying drawingswhich are given by way of illustration only, wherein like referencenumerals designate corresponding parts in the various drawings, andwherein

[0012]FIG. 1 depicts the signal encode, transmit, receive and decodeprocess according to one embodiment of the present invention; and

[0013]FIG. 2 depicts the padding unit and interleaver processoraccording to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]FIG. 1 depicts an example of the signal transmit and receiveprocess relative to encoding and decoding data using an embodiment ofthe method of this invention.

[0015] A source 1 generates a signal including data blocks of a numberof bits. Each data block may have an equal number of bits or data blocksof varying numbers of bits may be generated. The source 1 may be anysignal generator well known in the art. A turbo encoder 3 encodes thebits and data blocks by methods that are well known in the art and as aresult, no further description is provided. Once the data blocks areencoded, the data bits are referred to as symbols because the bits maybe corrupted during encoding, modulation and transmission.

[0016] The signal is then modulated by modulation unit 5, which may beany modulation unit well known in the art. Channel 7 is utilized duringtransmission of the encoded data. For example, channel 7 may be an airinterface. A demodulator unit 9 receives and demodulates the signal. Thedemodulator unit 9 may be any suitable demodulator unit well known inthe art. A padding unit 11 places the demodulated data blocks into abuffer 47 (as shown in FIG. 2) and if necessary, pads the data blocks.Additionally, the interleaver processor 55 supplies a padded interleavertable corresponding to the padded data block to the padding unit. Aturbo decoder 13 decodes the data block using the padded interleavertable. The turbo decoder 13 may be any suitable turbo decoder in theart. Lastly, the decoded data blocks are sent to the appropriate sink 15for storage or use.

[0017]FIG. 2 illustrates an embodiment of the padding unit 11 in detail.The padding unit includes a counter 49, compare unit 51, buffer 47, acontroller 41 and a padding position unit 43 and padding pattern unit45. An interleaver processor 55 and storage unit 53 are also depicted inFIG. 2.

[0018] The encoded data block 39 enters the padding unit 11 and thecounter 49 begins operation by counting the number of symbols N in thedata block. The counter 49 then communicates the number of symbols N tothe compare unit 51 and the compare unit 51 determines whether or not Nis greater than, equal to, or less than a threshold M, which is theminimum number of symbols required in a data block for proper operationof the decoder. The compare unit 51 notifies the controller 41 of therelationship between N and M.

[0019] Once the symbols in the encoded data block 39 are counted, thecounter 49 places the encoded data block 39 into buffer 47. If thecompare unit 51 determined that N is greater than or equal to M, thenthe controller 41 allows the data to be output to the decoder 13. On theother hand, if the compare unit 51 determined that N is less than M,then the controller 41 begins the padding operation and pads the symbolsin buffer 47 by adding padding symbols X such that N+X=M. Additionally,the controller 41 notifies the interleaver processor 55 of the number ofdata symbols N in the data block and the positioning of the paddingsymbols in the buffer relative to the data symbols.

[0020] It is preferable to pad the data blocks with less than M datasymbols in such a manner as to minimize performance loss with respect tothe case where no padding is performed. As shown in FIG. 2, the paddingunit 11 includes a padding position unit 43 and a padding pattern unit45, which assist the controller 41 in performing the padding.

[0021] The padding position unit 43 contains the instructions as towhere to place the padding symbols in the buffer 47. There are threetypes of padding positions. “Back padding” refers to inserting all thepadding symbols X into the buffer 47 after or behind the end of the datasymbols N of the encoded data block 39. The second type of padding iscalled “middle padding” and refers to inserting padding symbols X intothe buffer 47 between the data symbols N of the encoded data block 39.The third type of padding is called “front padding” and refers toinserting all the padding symbols X into the buffer 47 in front of thedata symbols N of the encoded data block 39.

[0022] Of the three padding positions, front padding or back padding arepreferred because insertion of the padding symbols in the middle of thedata block will puncture the data block and create a resulting loss ofperformance. Additionally, to place padding symbols in any of the abovepositions, it may be necessary to move the encoded data block 39 or aportion thereof within the buffer 47 in order to free the appropriatespace in the buffer 47 for the padding symbols.

[0023] A padding pattern unit 45 directs the specific padding symbols tobe used to pad the data block. Although the padding pattern mayincorporate a symbol representing any number as a padding symbol, theoptimum padding symbols for back padding have been determined to besymbols representing zeros, and the optimum padding symbols for frontpadding have been determined to be symbols representing negativeinfinity (e.g., −1,000,000).

[0024] For each block of padding symbols, the desired padding positionand padding symbols are preset in the padding algorithm unit 43 andpadding pattern unit 45 prior to operation of the decoder 13 for eachdata block. However, the invention is not limited to the preset paddingpositions and symbols. Both the padding symbol and pattern may bechanged for subsequent blocks of padding symbols, if others become moredesirable.

[0025] Additionally, when the number of data symbols in the data blockis less than M the controller 41 notifies the interleaver processor 55of the number of data symbols N in the data block and the positioning ofthe padding symbols in the buffer 47 relative to the data symbols.

[0026] The interleaver processor 55 has a storage unit 53, whichcontains a padded interleaving table corresponding to each of thepossible combinations of data symbols and padding symbols with respectto positioning and number. Since padding only occurs for data blockswith less than M data symbols, an interleaver table is stored for eachpossible number of data symbols such as 1 through M and for each numberof data symbols a separate table is stored for each possible position ofpadding symbols. Each interleaving table includes M bits, which includesinterleaving bits D and padding bits F, where M=D+F.

[0027] The interleaver processor 55 selects the interleaving table fromstorage unit 53 that corresponds to the padded data block. For example,if the padded data block has a total of 80 data symbols and 40 paddingsymbols positioned by back padding, an interleaving table is selectedwith 80 interleaving bits and 40 padding symbols positioned by backpadding.

[0028] The interleaver processor 55 transfers the selected paddedinterleaver table to the controller 41 and the controller 41 outputs thepadded interleaver table and the padded data block to the decoder 13.

[0029] The operation of a turbo decoder 13 is well known in the art, andtherefore is not described in detail. However, in a preferredembodiment, the method of turbo decoding is different with reference tothe use of interleaving tables. For example, as discussed above when thedata symbols in the data block are padded, a corresponding paddedinterleaver table is selected by the interleaver processor and output tothe decoder 13 by the padding unit 11. As a result, when the number ofdata symbols in a data block is less than M, the decoder 13 uses apadded interleaver table to decode the data. When the number of datasymbols in a data block is greater than or equal to M the decoderfunctions by using an unpadded interleaving table as is well known inthe art.

[0030] Upon completion of the decoding process, the decoder 13 outputs adata block including data bits substantially equivalent to the data bitsin the data block prior to encoding.

[0031] The addition of the padding symbols to encoded data blocks untilthe total number of symbols (N+X) is equal to the threshold M,essentially tricks the decoder 13 into decoding with improvedperformance because the total number of data symbols passed to thedecoder 13 is at least equal to M.

[0032] The invention being thus described, it will be obvious that thesame may be varied in many ways. Such variations are not to be regardedas a departure from the spirit and scope of the invention, and all suchmodifications are intended to be included within the scope of thefollowing claims.

We claim:
 1. A method of decoding received data block, said methodcomprising: receiving a symbol block of at least one data symbol,wherein each data symbol corresponds to an encoded data bit; padding thesymbol block with at least one padding symbol; and decoding the paddedsymbol block using a decoder.
 2. The method of claim 1, wherein thereceiving step receives the symbol block and places the symbol blockinto a buffer; and the padding step pads the symbol block by placing atleast one padding symbol into the buffer before the symbol block.
 3. Themethod of claim 1, wherein the receiving step receives the symbol blockand places the symbol block into a buffer; and the padding step pads thesymbol block by placing at least one padding symbol into the bufferafter the symbol.
 4. The method of claim 1, wherein the receiving stepreceives the symbol block and places the symbol block into a buffer; andthe padding step pads the symbol block by placing at least one paddingsymbol into the buffer in between at least two symbols in symbol block.5. The method of claim 1, the padding symbol substantially representszero, and negative infinity.
 6. The method of claim 1, furthercomprising providing a plurality of padded interleaver tables includingone first entry associated with each data symbol in the symbol block andone second entry associated with each padding symbol, wherein a firstpadded interleaver table of the plurality of padded interleaver tableshas a first number of first entries, a second padded interleaver of theplurality of padded interleaver tables has a second number of firstentries, and the decoding step includes sending the padded symbol blockwith N data symbols and the padded interleaver table with D firstentries to the decoder, where N=D.
 7. A method of decoding datacomprising: receiving a block of data symbols wherein the block includesat least one data symbol and each data symbol represents an encoded databit; determining if the block data symbols has a number of data symbolsequal to a threshold value M; if the number of data symbols is less thanM, padding the block of data symbols with at least one padding symbol;and decoding the padded block of data symbols.
 8. The method of claim 7,wherein the determining step counts the data symbols in the block ofdata symbols and compares the counted number to the threshold value M.9. The method of claim 7, wherein the receiving step receives the blockof data symbols and places the data symbols into a buffer; and thepadding step pads the block of data symbols by placing at least onepadding symbol into the buffer before the block data symbols.
 10. Themethod of claim 7, wherein the receiving step receives the block of datasymbols and places the data symbols into a buffer; and the padding steppads the block of data symbols by placing padding symbols into thebuffer after the block data symbols.
 11. The method of claim 7, whereinthe receiving step receives the block of data symbols and places thedata symbols into a buffer; and the padding step pads the block of datasymbols by placing padding symbols into the buffer in between at leasttwo data symbols in the block of data symbols.
 12. The method of claim7, wherein the padding bits substantially represent zero and negativeinfinity.
 13. The method of claim 7, further comprising providing aplurality of padded interleaver tables including a number of firstentries D including a first entry associated with each data symbol and asecond entry associated with each padding symbol, wherein a first paddedinterleaver table of the plurality of padded interleaver tables has afirst number of first entries, a second padded interleaver of theplurality of padded interleaver tables has a second number of firstentries, the number of data symbols in the block of data symbols is N,and if the number of data symbols N is less than M, the decoding stepincludes sending the padded block of data symbols with N data symbolsand the padded interleaver table with D decoding symbols to the decoder,where N=D.
 14. A decoding system comprising: a buffer for receiving asymbol block wherein the symbol block has at least one symbol and eachsymbol represents an encoded data bit; an interleaver unit containing aplurality of padded interleaver tables; a padding unit for creatingpadded symbol blocks by adding padding symbols to the buffer containingthe symbol block; and a decoder for decoding the padded symbol blocks.15. The decoding system of claim 14, wherein the decoder is a turbodecoder including at least two decoder units connected in series, and afirst decoder unit receives and processes the padded symbol block andgenerates a first output and a second decoder receives and processes thefirst output and generates a second output including decoded data. 16.The decoding system of claim 14, further comprising: a counter forcounting a number of data symbols N in the symbol block, a comparingunit for comparing N to a threshold number M of symbols required foroperation of the decoder; wherein the padding unit places paddingsymbols into the buffer, if the comparing unit indicates N is less thanM.
 17. The decoding system of claim 14, wherein the padding unit placespadding symbols into the buffer before the symbol block, after thesymbol block, or in between two symbols in the symbol block.
 18. Thedecoding system of claim 14, wherein the padding symbols substantiallyrepresent zero and negative infinity.
 19. The decoding system of claim14, wherein the interleaver unit includes a first padded interleavertable of the plurality of padded interleaver tables having a firstnumber of first entries D associated with the data symbols and a secondnumber of second entries associated with the padding symbols, and asecond padded interleaver of a plurality of padded interleaver tableshaving a third number of first entries D associated with the datasymbols and a fourth number of second entries associated with thepadding symbols.
 20. The decoding system of claim 14, wherein eachpadded interleaver table of the plurality of padded interleaver tableshas a first number of first entries D associated with the data symbolsand a second number of second entries associated with the paddingsymbols, the symbol block has a third number of data symbols N, and thedecoder performs decoding using the padded symbol block and a paddedinterleaver table, where N=D.